Processor chips have evolved significantly in recent decades. The advent of multi-core chips has enabled parallel computing and other functionality within computing devices including personal computers and servers. Processors were originally developed with only one core. Each core can be an independent central processing unit (CPU) capable of reading executing program instructions. Dual-, quad-, and even hexa-core processors have been developed for personal computing devices, while high performance server chips have been developed with upwards of ten, twenty, and more cores. Cores can be interconnected along with other on-chip components utilizing an on-chip interconnect of wire conductors or other transmission media. Scaling the number of cores on a chip can challenge chip designers seeking to facilitate high-speed interconnection of the cores. A variety of interconnect architectures have been developed including ring bus interconnect architectures, among other examples.
Computing devices can utilize interconnect architectures such as Peripheral Component Interconnect (PCI) Express (PCIe), to facilitate intercommunication between components on the device. An interconnect architecture can use credit-based flow control and other flow control rules to manage “fair” access and usage by the various component of the device to resources of the device. As components compete for resources, access of one component to the resources can suffer due to this competition or other factors. For instance, deadlock or livelock conditions can occur resulting in resource starvation of the deprived component. The same device is also able to issue responses to transactions for which it is the target in a timely manner. Internal starvation mechanisms have been developed for handling instance where a request or response of a component of a computing device fails to make forward progress. Forward progress in this context relates to a component's ability to issue transaction requests (or completion responses) and have them completed (or successfully delivered) in a timely manner. Forward progress can be stalled for a variety of reasons, such as when a device does not have flow control credits to successfully issue packets onto the link, among other examples.
Like reference numbers and designations in the various drawings indicate like elements.